Supply droop-induced clock phase shifts cause significant eye margin loss in source-synchronous IOs that are based on unmatched receiver (RX) clocking architectures. An eye diagram illustrates the eye margin. A data eye diagram is put together by folding parts of a data waveform corresponding to each individual data bit into a single graph with signal amplitude on the vertical axis and time on horizontal axis. The data bit is the data being transmitted or received at a node. By repeating this construction over many samples of the waveform, the resultant graph represents average statistics of the signal and resembles an eye. The eye opening corresponds to a 1-bit period and is called a Unit Interval (UI) width of the eye diagram. An ideal eye diagram exhibits sharp rise and fall times and a constant amplitude. The data is sampled by placing a sampling clock edge in the middle of the eye. With power supply voltage and/or current droop, the unmatched RX may suffer from mismatch in data and clock propagation delays. For example, unmatched RX architectures where clock and data paths may not have matched propagation delays, have a low power advantage compared to matched architectures, but large supply droops can significantly shift a trained sampling clock strobe edge with respect to the data eye. This shifted clock strobe edge reduces IO timing margin.